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영문 논문지

홈 홈 > 연구문헌 > 영문 논문지 > JSTS (Journal of Semiconductor Technology and Science)

JSTS (Journal of Semiconductor Technology and Science)

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한글제목(Korean Title) Design of 1-Kb eFuse OTP Memory IP with Reliability Considered
영문제목(English Title) Design of 1-Kb eFuse OTP Memory IP with Reliability Considered
저자(Author) Jeong-Ho Kim   Du-Hwi Kim   Liyan Jin   Pan-Bong Ha   Young-Hee Kim  
원문수록처(Citation) VOL 11 NO. 02 PP. 0088 ~ 0094 (2011. 06)
한글내용
(Korean Abstract)
영문내용
(English Abstract)
In this paper, we design a 1-kb OTP (Onetime programmable) memory IP in consideration of BCD process based EM (Electro-migration) and resistance variations of eFuse. We propose a method of precharging BL to VSS before activation of RWL (Read word-line) and an optimized design of read NMOS transistor to reduce read current through a non-programmed cell. Also, we propose a sensing margin test circuit with a variable pull-up load out of consideration for resistance variations of programmed eFuse. Peak current through the non-programmed eFuse is reduced from 728 μA to 61 μA when a simulation is done in the read mode. Furthermore, BL (Bit-line) sensing is possible even if sensed resistance of eFuse has fallen by about 9 kΩ in a wafer read test through a variable pull-up load resistance of BL S/A (Sense amplifier).
키워드(Keyword) eFuse   OTP   electro-migration   variable pull-up resistance  
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