JSTS (Journal of Semiconductor Technology and Science)
Current Result Document : 2 / 3
| 한글제목(Korean Title) |
Energy-efficient Custom Topology Generation for Linkfailure- aware Network-on-chip in Voltage-frequency Island Regime |
| 영문제목(English Title) |
Energy-efficient Custom Topology Generation for Linkfailure- aware Network-on-chip in Voltage-frequency Island Regime |
| 저자(Author) |
Chang-Lin Li
Jae-Chern Yoo
Tae Hee Han
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| 원문수록처(Citation) |
VOL 16 NO. 06 PP. 0832 ~ 0841 (2016. 12) |
한글내용
(Korean Abstract) |
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영문내용
(English Abstract) |
The voltage-frequency island (VFI) design paradigm has strong potential for achieving high energy efficiency in communication centric manycore system-on-chip (SoC) design called network-on-chip (NoC). However, because of the diminished scaling of wire-dimension and supply voltage as well as threshold voltage in modern CMOS technology, the vulnerability to link failure in VFI NoC is becoming a crucial challenge. In this paper, we propose an energy-optimized topology generation technique for VFI NoC to cope with permanent link failures. Based on the energy consumption model, we exploit the onchip communication traffic patterns and characteristics of link failures in the early design stage to accommodate diverse applications and architectures. Experimental results using a number of multimedia application benchmarks show the effectiveness of the proposed three-step custom topology generation method in terms of energy consumption and latency without any degradation in the fault coverage metric.
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| 키워드(Keyword) |
Voltage-frequency island
network-onchip
link failure
custom topology generation
energy optimization
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| 원문 |
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